1b--route_details

2009-05-13 14:09:44来源:未知 阅读 ()

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Route details:
1. the common wire wideth is 1.1524mm.
   so I will set my wideth the same value,
   and the clearence to be 1.6mm.
2. if you right click the workspace
   and choose interactive route,
   then you are not allowed to  connect items of different nets.
   But if you choose Place|line, you can connect anything. Clever!
3. route as the sch file!! Things get clear!
4. in big circuits, there are many Capaictors and resistors with same labels VDD and GND,
   but be sure to put them where they shall be,
   otherwise, they won’t work as expected.
5. the GND pin requires a fun out, a via is needed
   otherwise the polygon can not reach it due to too many lines around.
6. when placing polygon,
   it is necessary to select pour over same
   and remove dead copper,
   you can not do it successary without the two option.
DRC
1. open a pcb file,
   right click in the work space and choose rules,
   then you can set your rules and run your check,
CREAT NETLIST
1. if you want to connect pins with same lable,
   you have to choose net lables and ports globe.!!!
2. it is so strange that in a net list my U_j_e 14 shows up in two nets:
   vcc and vdd3.3
   but luckly when loaded into pcb file the vcc net is empty
   and the pin14 is connected to vdd33.
   how can this happen?
   Vcc is nothing but the pin name of the component in sch lib.
   But usually the pin name does not affect the net name,
   it is the pin number here that matters.
3. but anyway it does not bring error in pcb,
   so I do not have to fix it.
   It just looks strange that there is a net VCC which contains no component.
4. it is more strange that
   when two pins with the same net name are not in a net like my XMON!!!
   But this trouble disappears
   when I do the same thing again,
   this teach me a good lesson!
   The final check is the only thing you can trust if any.
5. but sometimes it is your own fault.
   VDD33 is not VDD33V nor VDD3.3.
   but this mistake can easily be found by a look at the list of nets.
6. when the net GND is still devided into many subnets after placing polygon,
   don’t worry.
   There will be the green lines to connect each stand along net.
   Find them and place more lines and vias.

本文来自ChinaUnix博客,如果查看原文请点:http://blog.chinaunix.net/u1/56913/showart_973819.html

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